设计了一个14位40 MHz、100 dB SFDR、1.8 V电源电压的流水线A/D转换器(ADC)。采用增益自举密勒补偿两级运放,可在保证2Vp-p差分输出信号摆幅的前提下获得130dB的增益,有效地减小了运放有限增益的影响;同时,采用冗余位编码技术和动态比较器,降低了比较器失调电压的设计难度和功耗。该设计采用UMC 0.18μm CMOS工艺,芯片面积为2mm×4 mm。仿真结果为:输入满幅单频9 MHz的正弦信号,可以达到100 dB SFDR和83.8 dBSNDR。 A 14-bit, 40 MHz, 100 dB SFDR, 1.8-V supply A / D converter (ADC) is designed. The use of gain bootstrap Miller compensation of two op amps can be obtained in the premise of 2Vp-p differential output signal swing gain of 130dB, effectively reducing the operational amplifier limited gain; the same time, redundant bit encoding Technical and dynamic comparators reduce the design complexity and power consumption of the comparator offset voltage. The design uses UMC 0.18μm CMOS technology, the chip area of ​​2mm × 4mm. The simulation result is: Input full-scale 9 MHz single-frequency sine signal, can reach 100 dB SFDR and 83.8 dBSNDR.