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A new mixed curvature compensation technique for CMOS voltage reference is presented, which resorts to two sub-references with complementary temperature characteristics. The first sub-reference is the source–gate voltage︱VGS︱_p of a PMOS transistor working in the saturated region. The second sub-reference is the weighted sum of gate–source voltages︱VGS︱_n of NMOS transistors in the subthreshold region and the difference between two base–emitter voltages △V_(BE) of bipolar junction transistors(BJTs). The voltage reference implemented utilizing the proposed curvature compensation technique exhibits a low temperature coefficient and occupies a small silicon area.The proposed technique was verified in 0.18 μm standard CMOS process technology. The performance of the circuit has been measured. The measured results show a temperature coefficient as low as 12.7 ppm/℃ without trimming,over a temperature range from -40 to 120 ℃, and the current consumption is 50 μA at room temperature. The measured power-supply rejection ratio(PSRR) is 31:2 dB @ 100 kHz. The circuit occupies an area of 0.045 mm~2.
A new mixed curvature compensation technique for CMOS voltage reference is presented, which resorts to two sub-references with complementary temperature characteristics. The first sub-reference is the source-gate voltage | VGS | _p of a PMOS transistor working in the saturated region. The second sub-reference is the weighted sum of gate-source voltages | VGS | -n of NMOS transistors in the subthreshold region and the difference between two base-emitter voltages ΔV_ (BE) of bipolar junction transistors (BJTs). The voltage reference implemented utilizing the proposed curvature compensation technique exhibits a low temperature coefficient and occupies a small silicon area. The proposed technique was verified in 0.18 μm standard CMOS process technology. The performance of the circuit has been measured. The measured results show a temperature coefficient as low as 12.7 ppm / ° C without trimming, over a temperature range from -40 to 120 ° C, and the current consumption is 50 μA at room The measured power-supply rejection ratio (PSRR) is 31: 2 dB @ 100 kHz. The circuit occupies an area of 0.045 mm ~ 2.