This paper proposes a new multi-stage parallel interference cancellation scheme by modifying the conventional multi-stage parallel interference canceller (PIC). At each stage, it first converts the interference-cancelled outputs from previous stage into the a prior information, in terms of which the bit mean values are computed and the multi-access interference (MAI) for each user is evaluated, and then an interference cancellation is performed to obtain further interference suppression. To reduce the implementation complexity, we give an approximation expression for bit mean value. The performance over AWGN channel is analyzed and compared to the conventional PIC. The user number K=7 and spreading factor N=13 are chosen as simulation parameters. The computer simulation results show that the proposed PIC has better performance than the conventional PIC both with 2 interference cancellation (IC) stages, at bit error rate of 10 -3, for example, about 3 dB performance gain is obtained by using the proposed PIC. It is also shown that our proposed PIC with 1-stage is superior to the conventional PIC with 2-stage in performance, which is of practical value because PIC with fewer stages can bring about shorter processing delay. This paper proposes a new multi-stage parallel interference cancellation scheme by modifying the conventional multi-stage parallel interference canceller (PIC). At each stage, it first converts the interference-canceled outputs from previous stage into the a prior information, in terms of which the bit mean values ​​are computed and the multi-access interference (MAI) for each user is evaluated, and then an interference cancellation is performed to obtain further interference suppression. To reduce the implementation complexity, we give an approximation expression for bit mean value The performance over AWGN channel is analyzed and compared to the conventional PIC. The user number K = 7 and spreading factor N = 13 are chosen as simulation parameters. The computer simulation results show that the proposed PIC has better performance than the conventional PIC both with 2 interference cancellation (IC) stages, at bit error rate of 10 -3, for example, about 3 dB performance gain is obtained by using the proposed PIC. It is also shown that our proposed PIC with 1-stage is superior to the conventional PIC with 2-stage in performance, which is practical value because PIC with fewer stages can bring about shorter processing delay.