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This paper presents a single-ended 8-channel 10-bit 200 kS/s 607W synchronous successive approximation register(SAR) analog-to-digital converter(ADC) using HLMC 55 nm low leakage(LL) CMOS technology with a 3.3V/1.2V supply voltage.In conventional binary-encoded SAR ADCs the total capacitance grows exponentially with resolution.In this paper a CR hybrid DAC is adopted to reduce both capacitance and core area.The capacitor array resolves 4 bits and the other 6 bits are resolved by the resistor array.The 10-bit data is acquired by thermometer encoding to reduce the probability of DNL errors which are typically present in binary weighted architectures.This paper uses an auto-zeroing offset cancellation technique that can reduce the offset to 0.286 m V.The prototype chip realized the 10-bit SAR ADC fabricated in HLMC 55 nm CMOS technology with a core area of 16787 m2.It shows a sampling rate of 200 k S/s and low power dissipation of 607 W operates at a 3.3 V analog supply voltage and a 1.2 V digital supply voltage.At the input frequency of 10 k Hz the signal-to-noise-anddistortion ratio(SNDR) is 60.1 d B and the spurious-free dynamic range(SFDR) is 68.1 d B.The measured DNL is C0:37/0:06 LSB and INL is C0:58/0:22 LSB.
This paper presents a single-ended 8-channel 10-bit 200 kS / s 607W synchronous serial approximation register (SAR) analog-to-digital converter 1.2V supply voltage. Conventional binary-encoded SAR ADCs the total capacitance grows exponentially with resolution. This paper a CR hybrid DAC is adopted to reduce both capacitance and core area. The capacitor array resolves 4 bits and the other 6 bits are resolved by the resistor array. The 10-bit data is acquired by thermometer encoding to reduce the probability of DNL errors which are typically present in binary weighted architectures. This paper uses an auto-zeroing offset cancellation technique that can reduce the offset to 0.286 mV The prototype chip realized the 10-bit SAR ADC fabricated in HLMC 55 nm CMOS technology with a core area of 16787 m2.It shows a sampling rate of 200 k S / s and low power dissipation of 607 W at at 3.3 V analog supply voltage and a 1.2 The signal-to-noise-and-distortion ratio (SNDR) is 60.1 d B and the spurious-free dynamic range (SFDR) is 68.1 d B. The measured DNL is C0: 37/0: 06 LSB and INL is C0: 58/0: 22 LSB.