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A novel dry etching process of a poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor(CMOS) devices is investigated.Our strategy to process a poly-Si/TaN/HfSiON gate stack is that each layer of gate stack is selectively etched with a vertical profile.First,a three-step plasma etching process is developed to get a vertical poly-Si profile and a reliable etch-stop on a TaN metal gate.Then different BCl_3-based plasmas are applied to etch the TaN metal gate and find that BCl_3/Cl_2/O_2/Ar plasma is a suitable choice to get a vertical TaN profile.Moreover,considering that Cl_2 almost has no selectivity to Si substrate, BCl_3/Ar plasma is applied to etch HfSiON dielectric to improve the selectivity to Si substrate after the TaN metal gate is vertically etched off by the optimized BCl_3/Cl_2/O_2/Ar plasma.Finally,we have succeeded in etching a poly-Si/TaN/HfSiON stack with a vertical profile and almost no Si loss utilizing these new etching technologies.
A novel dry etching process of a poly-Si / TaN / HfSiON gate stack for advanced complementary metal-oxide-semiconductor (CMOS) devices is investigated. Our strategy to process a poly-Si / TaN / HfSiON gate stack is that each layer of gate stack is selectively etched with a vertical profile. First, a three-step plasma etching process is developed to get a vertical poly-Si profile and a reliable etch-stop on a TaN metal gate. Different BCl_3-based plasmas are applied to etch the TaN metal gate and find that BCl_3 / Cl_2 / O_2 / Ar plasma is a suitable choice to get a vertical TaN profile. Moreover, considering that Cl_2 has almost no selectivity to Si substrate, BCl_3 / Ar plasma is applied to etch HfSiON dielectric to improve the selectivity to Si substrate after the TaN metal gate is vertically etched off by the optimized BCl_3 / Cl_2 / O_2 / Ar plasma.Finally, we have succeeded in etching a poly-Si / TaN / HfSiON stack with a vertical profile and almost no Si loss utilizing these new etching technologies.