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A low power 10-bit 250 MSPS charge-domain(CD) pipelined analog-to-digital converter(ADC) is introduced.The ADC is implemented in MOS bucket-brigade devices(BBDs) based CD pipelined architecture.A replica controlled boosted charge transfer(BCT) circuit is introduced to reject the influence of PVT variations on the charge transfer process.Based on replica controlled BCT,the CD pipelined ADC is designed and realized in a1P6 M 0.18 μm CMOS process.The ADC achieves an SFDR of 64.4 dB,an SNDR of 56.9 dB and an ENOB of9.2 for a 9.9 MHz input;and an SFDR of 63.1 dB,an SNR of 55.2 dB,an SNDR of 54.5 dB and an ENOB of 8.7for a 220.5 MHz input at full sampling rate.The DNL is +0.5/- 0.55 LSB and INL is +0.8/- 0.85 LSB.The power consumption of the prototype ADC is only 45 mW at 1.8 V supply and it occupies an active die area of 1.56mm~2.
A low power 10-bit 250 MSPS charge-domain (CD) pipelined analog-to-digital converter (ADC) is introduced. The ADC is implemented in a MOS buck-mounted devices (BBDs) based CD pipelined architecture. A replica controlled boosted charge transfer (BCT) circuit is introduced to reject the influence of PVT variations on the charge transfer process. Based on replica controlled BCT, the CD pipelined ADC is designed and realized in a1P6 M 0.18 μm CMOS process. The ADC achieves an SFDR of 64.4 dB an SNDR of 56.9 dB and an ENOB of 9.2 for a 9.9 MHz input; and an SFDR of 63.1 dB, an SNR of 55.2 dB, an SNDR of 54.5 dB and an ENOB of 8.7 for a 220.5 MHz input at full sampling rate The DNL is + 0.5 / - 0.55 LSB and INL is + 0.8 / - 0.85 LSB. The power consumption of the prototype ADC is only 45 mW at 1.8 V supply and it occupies an active die area of 1.56 mm ~ 2.