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通常,I~2L门的传播延迟时间随着注入管电流的增加而减小。这是因为耗尽层结电容更迅速充放电的结果。可是,在中等电流范围内,由于有源晶体管电荷存储的增加,延迟时间开始饱和。由于开关管基区比基区下面剩余的外延层部分是更重的掺杂,电荷存储的主要部分在这后面的区域中,而且在常规的I~2L中,pnp注入管基区内的存储比npn管少很多,在这些条件下,给出了最小的延迟时间t_d为(见I_1,方程(18)和(21)])
In general, I ~ 2L gate propagation delay time decreases as the injector current increases. This is due to the depletion of the junction capacitance more rapidly as a result of charging and discharging. However, in the medium current range, the delay time begins to saturate due to the increased charge storage in the active transistor. Since the switch base region is more heavily doped than the remaining portion of the epitaxial layer below the base region, the major portion of charge storage is in this latter region, and in conventional I-2L, the storage of pnp into the base region Much less than npn tubes, the minimum delay time t_d is given under these conditions (see I_1, equations (18) and (21)])