随着片上网络的发展,片上多处理器系统通信性能提高的同时,存储器的访问性能将成为片上多处理器系统的性能瓶颈.目前片上网络的研究主要依赖于模拟器,而现有的片上网络模拟器都不能完成对存储器访问的准确模拟.本文设计并实现了一个能对存储器访问进行模拟的模拟器,为存储器性能的研究提供了一个实验平台;论文通过采用大量访问集对该模拟器进行测试,得出了若干条与存储器访问性能优化相关的片上网络设计建议. With the development of on-chip network and the improvement of on-chip multiprocessor system communication performance, the access performance of memory will become the performance bottleneck of multi-processor system on chip.Currently the research of on-chip network mainly depends on the simulator, while the existing on-chip network The simulator can not complete the accurate simulation of memory access.This paper designs and implements a simulator that can simulate the memory access and provides an experimental platform for the research of memory performance.The paper uses a large number of access sets to simulate the simulator Test, come to a number of memory access performance optimization related to on-chip network design recommendations.