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为解决当前固态存储系统有效适应大规模数据高速存储的问题,以NAND Flash为存储介质,利用循环SRAM缓冲、多体存储阵列、交叉开关矩阵等技术实现了低速Flash芯片阵列构建的嵌入式高速数据存储机制.其中SRAM缓冲阵列采用了读写分组和循环管理,Flash阵列采用并行双总线架构、分组交叉编址和多级流水线技术,同时利用基于总线开关的交叉矩阵对两个阵列进行连接,提高了系统的读写带宽并增强了系统可扩展性.理论分析和仿真实验结果表明:该存储机制能够有效适用于嵌入式大规模数据的存储,对Flash读写操作的最大加速比将近20倍,具有良好的数据访问性能.
In order to solve the problem that the current solid-state storage system is effectively adapted to the large-scale data high-speed storage, the embedded high-speed data constructed by the low-speed Flash chip array is implemented by using the NAND Flash as a storage medium and using the technologies of a circular SRAM buffer, a multi-body memory array and a crossbar switch matrix Storage mechanism.Among them, SRAM buffer array adopts read-write grouping and loop management, Flash array adopts parallel dual-bus architecture, packet cross-addressing and multi-stage pipeline technology, meanwhile, it uses bus matrix based on bus switch to connect two arrays to improve The system read and write bandwidth and enhance the system scalability.The theoretical analysis and simulation results show that: The storage mechanism can be effectively applied to the storage of embedded large-scale data, the maximum speedup of Flash read and write operations nearly 20 times, Has good data access performance.