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源耦合FET逻辑(SCFL)电路是为千兆位数字信号处理而提出来的。本文介绍了SCFL电路中FET阈值电压的容限和SCFL电路的性能。SCFL门速度取决于其中FET的工作范围。为实现高速,必须提供一个高于夹断电压的FET源漏电压。预计由1.5μm栅长FET构成的SCFL门最小延迟时间共达25ps/门,最小上升时间与下降时间分别可达54ps和51ps,最大RZ数据速率可达5.6Gb/s。SCFL电路可用于高速数字信号处理。
The source-coupled FET logic (SCFL) circuit is proposed for gigabit digital signal processing. This article describes the tolerance of FET threshold voltage in SCFL circuits and the performance of SCFL circuits. The speed of the SCFL gate depends on the operating range of the FET. To achieve high speed, FET source and drain voltages must be provided above the pinch-off voltage. The SCFL gate with a 1.5μm gate-length FET is expected to have a minimum delay of 25ps / gate with minimum rise and fall times of 54ps and 51ps, respectively, and a maximum RZ data rate of 5.6Gb / s. SCFL circuit can be used for high-speed digital signal processing.