Field plate(FP)-terminated 4H-SiC trench gate MOSFETs are demonstrated in this work.N+/P?/N?/N+multiple epitaxial layers were grown on 3-inch N+type 4H-SiC substrate by chemical vapor deposition(CVD),and then the 4H-SiC trench gate MOSFETs were fabricated based on the standard trench transistor fabrication.Current-voltage measurements in forward and reverse bias have been performed on different devices with and without FP protections.It is found that more than 60%of the devices protected with FP termination are able to block 850 V.The measurements also show that the devices have the small leakage currents 0.15 nA at 600 V and 2.5 nA at 800 V,respectively.The experimental results also were compared with the simulated results,which show good agreement with each other in the trend.The limited performance of the devices is mainly because of the damage induced on the trench sidewalls from the etching process and the quality of the SiO2 films.Therefore,the 4H-SiC trench gate MOSFETs are expected to be optimized by reducing the etching damage and growing high-quality SiO2 dielectric films. Field plate (FP) -terminated 4H-SiC trench gate MOSFETs are demonstrated in this work. N + / P? / N? / N + multiple epitaxial layers were grown on 3-inch N + type 4H-SiC substrate by chemical vapor deposition CVD), and then the 4H-SiC trench gate MOSFETs were fabricated based on the standard trench transistor fabrication. Current-voltage measurements in forward and reverse bias have been performed on different devices with and without FP protections. It is found that more than 60 % of the devices protected with FP termination are able to block 850 V. The measurements also show that the devices have the small leakage currents 0.15 nA at 600 V and 2.5 nA at 800 V, respectively. The experimental results also were compared with the simulated results, which show the good agreement with each other in the trend. the limited performance of the devices is mainly because of the damage induced on the trench sidewalls from the etching process and the quality of the SiO2 films. Beforefore, the 4H-SiC trench gate MOSFETs are expe cted to be optimized by reducing the etching damage and growing high-quality SiO2 dielectric films.