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当今VLIW DSP处理器拥有的指令种类越来越多,它们大多利用单一指令来完成一组复杂的计算,从而提高相关操作的执行效率.无论是在现有数字信号处理程序中,还是使用各种优化手段之后的程序代码中,累加计算在VLIW DSP处理器运算的程序中总是频繁出现,编译器如何自动高效地识别并合成处理器特有的累加指令就变得尤为重要.提出一种VLIW DSP处理器下累加计算优化方法,算法可以自动合成目标处理器的累加指令,充分利用处理器体系结构和资源的特点.最后在BWDSP处理器上实现本文的优化算法,实验结果表明,本算法有效减小了程序累加部分的汇编代码长度,从而提高了BWDSP对累加计算的处理能力.
Today’s VLIW DSP processors have more and more types of instructions, most of which use a single instruction to complete a complex set of computations to improve the execution efficiency of related operations. Whether in the existing digital signal processing programs, or using a variety of It is very important for the compiler to recognize and synthesize the processor-specific accumulative instructions automatically and efficiently in the program code after the optimization.Finally, a VLIW DSP The algorithm can accumulate the target processor’s accumulative instructions automatically and make full use of the characteristics of the processor architecture and resources.Finally, the optimization algorithm of this paper is implemented on the BWDSP processor.The experimental results show that this algorithm is effective in reducing The length of the assembly code of the accumulative part of the program is increased, thereby improving the processing capability of the BWDSP to the accumulative calculation.