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介绍并实现了一种高速32×32有符号/无符号二进制乘法器。该乘法器采用改进基4BOOTH算法编码方式,所产生的电路与传统相比减小了延时与面积,并采用符号补偿技术对每个部分积进行符号位补偿,进一步简化电路。该乘法器在关键路径上采用改进混合Wallace树压缩器阵列进行优化,其压缩器阵列对称有利于布局布线。该乘法器插入流水后能运行到250MHz,可用作专用数据通道的乘法单元。
Introduced and implemented a high-speed 32 × 32 signed / unsigned binary multiplier. The multiplier uses improved base 4BOOTH algorithm encoding, the resulting circuit reduces the delay and area compared with the traditional, and the use of symbol compensation for each partial product of the sign bit compensation, to further simplify the circuit. The multiplier is optimized on the critical path with an improved hybrid Wallace tree compressor array whose symmetry of the compressor array facilitates placement and routing. The multiplier can run to 250MHz after it is inserted into the pipeline and can be used as a multiplication unit for a dedicated data channel.