Because of the flexibility of program-mable devices as well as other merits, the EPLD(erasable programmable logic device) chip was usedto implement the matrix transformation of HDTVvideo signal. In this paper, Altera’s EPLD chipnamed EPM9400LC84-15 was used really. A seriesof computer simulations and optimizations are real-ized. First, the 54MHz processing speed was achievedby use of an improved carry-selection parallel addi-tion structure. Second, two kinds of technique, oneis the fine adjustment of transformation equations aswell as their coefficients, the other is the conversionof float point algorithm to fixed point algorithm, pre-vent precision from reducing and overflowing of mid-dle result. Third, many kinds of combined results of the different resource and precision requirements werecompared and evaluated on the last transformationoutput level, a good compromise result between chiplogic resource and transformation precision was finallyobtained. Furthermore, a concise correlation curvebetween them was illustrated in detail and a precisionequation was also defined using a 8 × 8-bit multiplier asan example. After simple improvement, this kind ofcorrelation approach can also be used to some similarEPLD designs and in other video processing fields.