为了实现更高性能的LSI,最近提出了自对准多晶硅电极工艺(SPEL).这种工艺采用优先干法刻蚀重掺杂多晶硅,使MOS和双极晶体管的接触区面积比常规工艺减少一半.而且晶体管的寄生电容和电阻也减小. In order to achieve higher performance LSIs, a self-aligned polysilicon electrode process (SPEL) has recently been proposed, which preferentially drills heavily doped polysilicon to reduce the contact area between MOS and bipolar transistors by half as compared to conventional processes And the parasitic capacitance and resistance of the transistor are also reduced.