根据CMOS电路动态功耗模型对格雷码计数器的分析,并在MAX+PlusⅡ环境用Verilog语言对其设计和仿真,从而得出gray16的仿真波形图。最后对格雷码计数器进行功耗分析,并在Modelsim环境下对其波形仿真证明,该分频器功耗降低的百分比随着分频数增加而起伏波动,当分频数最大(32分频)时功耗降低最多,其值和格雷码计数器相对于二进制计数器的功耗降低百分比相同。 According to the CMOS circuit dynamic power model Gray code counter analysis, and MAX + Plus Ⅱ environment with Verilog language design and simulation, resulting gray16 simulation waveform. Finally, the Gray code counter power analysis and simulation in the Modelsim environment waveform prove that the percentage of the frequency divider to reduce the power consumption fluctuations with the increase and fluctuation, when the maximum number of divisions (32) The consumption is reduced the most, and its value is the same as the percent reduction of the Gray code counter relative to the binary counter.