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介绍了静态时序分析在数字集成电路设计中的应用,并以100M以太网卡芯片设计为例,具体描述了以太网卡芯片设计中的静态时序分析流程及其时序问题。
The application of static timing analysis in the design of digital integrated circuits is introduced. Taking 100M Ethernet chip design as an example, the static sequence analysis process and its timing problem in the design of Ethernet chip are described in detail.