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目前,数字式锁相环只用于对接收信号进行载波相位跟踪,因而产生出适于同步解调的信号。如果用作调频解调,锁相环就要采用模拟电路结构。但是模拟电路设备有以下缺点:1.因所有锁相环的压控振荡器必须对相位输入改变频率,所以电路就成为一种积分器。模拟积分器总是“易漏的__”,也就是说,不是以线性形式对直流输入响应。2.鑑相器和放大器存在不准确性,闭环系统有杂散极点,这种不准确性是由相位检测过程需要相乘而引起的。可见,模拟乘积器对直流偏移很灵敏,任何偏移都成为误差加在乘积器的输入端。3.当输入载波噪声比很低时,噪声脉冲往往会引起锁相环部件的饱和。如果是这种输入方式,其环路宁可让信号“骑在”噪声上,而不让噪声“骑在”信号上。若压控振荡器因噪声脉冲而饱和,便失去在积分过程中原先信号存起来的所有信息。因此,当不再出现噪声脉冲时,环路就会像刚接收到系统功率时那样,转入开始截获信号的瞬变状态。4.如果让模拟环路由阶次更高的系统来实现时,寄生电容就会引起附加极点,由于噪声的存在,这个系统有可能成为一个不稳定的系统。为了避免这些问题,本文所讨论的锁相环,采用全数字电路来设计。在设计数字加法器、相乘器、计数器和滤波器的同时, 还设计了压控振荡器的计算方法。上述的问题解决了,但又有数字系统共性的新问题,这些问题包括以量化噪声形式出现的取成整数引起误差和过量误差。
At present, the digital phase-locked loop is only used for carrier phase tracking of the received signal, thus generating a signal suitable for synchronous demodulation. If used for FM demodulation, the PLL must use analog circuit structure. However, the analog circuit device has the following disadvantages: 1. The circuit becomes an integrator because all phase-locked loop voltage-controlled oscillators must change the frequency of the phase input. The analog integrator is always “leaky __”, that is, it does not respond to the DC input in linear form. 2. Phase detector and amplifier inaccuracy, closed-loop system has spurious poles, this inaccuracy is caused by the phase detection process needs to be multiplied. It can be seen that the analogue multiplier is sensitive to DC offsets and that any offset is added to the input of the multiplier. 3. When the input carrier to noise ratio is very low, noise pulses tend to cause phase-locked loop components to saturate. With this type of input, the loop would rather “signal” the signal rather than “ride on” the noise. If the voltage-controlled oscillator is saturated with a noise pulse, it loses all of the information it had previously stored in the integration process. Therefore, when the noise pulse no longer occurs, the loop transitions to the transient state where the interception of the signal begins, as it did when the system power was just received. 4. If the analog loop is implemented by a higher-order system, parasitic capacitances cause additional poles and the system may become an unstable system due to noise. In order to avoid these problems, the PLL discussed in this article, using all-digital circuit design. In the design of digital adders, multipliers, counters and filters, but also designed a voltage-controlled oscillator calculation method. The above problems have been solved, but there are also new problems common to digital systems. These problems include rounding errors and excessive errors in the form of quantization noise.