提出了一种利用窄脉冲发生器驱动输出级,以提高电路抗噪声能力,同时保持动态电路的高速特性的多输入动态逻辑电路.提出了这种电路的分析模型,用于说明电路的抗噪声特性和管子的参数设置.在0.18μmCMOS工艺,1.8V的Vdd电压和55℃的环境温度下,模拟结果表明:与现有的两种技术相比,在相同的最坏延时情况下,新结构具有更好的抗噪声能力,分别提升了12%和8%;而在具有相同的抗噪声能力的情况下,新结构具有更快的速度,分别提高了1.6倍和1.4倍. This paper presents a multi-input dynamic logic circuit which uses a narrow pulse generator to drive the output stage to improve the anti-noise ability of the circuit while maintaining the high-speed characteristics of the dynamic circuit. An analysis model of this circuit is proposed to illustrate the circuit’s anti-noise Characteristics and the parameters of the tube.With the 0.18μm CMOS process, the Vdd voltage of 1.8V and the ambient temperature of 55 ℃, the simulation results show that compared with the two existing technologies, under the same worst-case delay condition, The structure has better anti-noise ability, which is improved by 12% and 8% respectively; while with the same anti-noise ability, the new structure has a faster speed, increased 1.6 times and 1.4 times respectively.