论文部分内容阅读
首先介绍了硅纳米晶粒的制备工艺以及硅纳米晶存储器件的基本特性。接着重点探讨了硅纳米晶存储器耐久性退化的物理机制,发现应力引起的界面陷阱是耐受性退化的主要原因。随后,同时采用多种分析手段,如电荷泵法和CV曲线分析法对界面陷阱的退化机理进行了更深入细致的研究。从界面陷阱在禁带中的能级分布中发现,相较于未施加应力时界面陷阱的双峰分布,施加应力后产生了新的Pb1中心的双峰。最后,分别从降低擦写电压和对载流子预热的角度提出了三种新的编程方法,有效提高了硅纳米晶存储器件的耐受性。
First of all, the preparation process of silicon nanocrystals and the basic characteristics of silicon nanocrystalline memory devices are introduced. Then, the physical mechanism of the durability degradation of silicon nanocrystalline memory is discussed emphatically. It is found that the interface traps induced by stress are the main reasons for the degradation of the resistance. Subsequently, a variety of analytical methods, such as charge-pump method and CV curve analysis, were used to study the degradation mechanism of interface traps in more detail. From the energy level distribution of interface traps in the forbidden band, it is found that a new double peak at the center of Pb1 is produced when stress is applied compared to the bimodal distribution of interface traps when no stress is applied. Finally, three new programming methods are put forward to reduce the erase voltage and preheat carriers respectively, which effectively improves the tolerance of silicon nanocrystalline memory devices.