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本文研究了用低冗余成本可允许大量故障的一个存贮器结构。存贮器中基本的元件是 LSI 片同,由它实现一具字容量 y×位长 b,并带有 y 个字的地址译码器的存贮器部分。集成片<包括备份>经开关网络连结以便芯片在失效时存贮器可以有效地进行重构。本文有关开关网络的主要结论如下:1>.开关网络和备份片的附加成本与非冗余存贮器系统相比是低的。2>.在开关网络成本,容错失效的芯片备份片S 以及建立开关网络的复合体之间有界线清楚的折衷方案。3).为了增加存贮器的可靠性和一致性、开关网络可以封装在存贮器芯片内。我们同时也研究了存贮器结构系统的某些方面,建立开关网络和这种结构与字区替换结比较时的有关性能。索引术语——计算机存贮器、容错、LSI 存贮器,可重构存贮器,可靠性。
This paper studies a memory structure that allows a large number of faults with low redundancy costs. The basic element in the memory is the LSI chip, which implements a memory portion of an address decoder with a word size of y × bit length b and y words. The integrated circuit is connected via the switch network so that the memory can be effectively reconfigured in the event of a chip failure. The main conclusions of this paper about switch networks are as follows: 1> The added cost of switching networks and backups is low compared to non-redundant memory systems. 2> There is a clear trade-off between switching network costs, fault-tolerant chip backup S, and the establishment of switching network complexes. 3). In order to increase the reliability and consistency of the memory, the switching network can be encapsulated in the memory chip. We have also studied certain aspects of the memory fabric system to establish the switching network and the relative performance of such a structure when compared to the word-area replacement junction. Index Terms - Computer Memory, Fault Tolerance, LSI Memory, Reconfigurable Memory, Reliability.