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Single-event transient pulse quenching(Quenching effect)is employed to effectively mitigate WSET(SET pulse width).It enhanced along with the increased charge sharing which is norm for future advanced technologies.As technology scales,parameter variation is another serious issue that significantly affects circuit’s performance and single-event response.Monte Carlo simulations combined with TCAD(Technology Computer-Aided Design)simulations are conducted on a six-stage inverter chain to identify and quantify the impact of charge sharing and parameter variation on pulse quenching.Studies show that charge sharing induce a wider WSET spread range.The difference of WSET range between no quenching and quenching is smaller in NMOS(N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor)simulation than that in PMOS’(P-Channel Metal-Oxide-Semiconductor Field-Effect Transistor),so that from parameter variation view,quenching is beneficial in PMOS SET mitigation.The individual parameter analysis indicates that gate oxide thickness(TOXE)and channel length variation(XL)mostly affect SET response of combinational circuits.They bring 14.58%and 19.73%average WSET difference probabilities for no-quenching cases,and 105.56%and 123.32%for quenching cases.
Single-event transient pulse quenching (Quenching effect) is employed to effectively mitigate WSET (SET pulse width) .It enhanced along with the increased charge sharing which is norm for future advanced technologies. As technology scales, parameter variation is another serious issue that is significantly affecting circuit’s performance and single-event response. Monte Carlo simulations combined with TCAD (Technology Computer-Aided Design) simulations are conducted on a six-stage inverter chain to identify and quantify the impact of charge sharing and parameter variation on pulse quenching. that charge sharing induce a wider WSET spread range. The difference of WSET range between no quenching and quenching is smaller in NMOS (N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) simulation than that in PMOS ’(P-Channel Metal- Oxide-Semiconductor Field-Effect Transistor), so that from parameter variation view, quenching is beneficial in PMOS SET mitigation. Individual parameter ana Lysis indicates that gate oxide thickness (TOXE) and channel length variation (XL) only affect SET response of combinational circuits. They bring 14.58% and 19.73% average WSET difference probabilities for no-quenching cases, and 105.56% and 123.32% for quenching cases .