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设计了一种10 bit 40 MS/s流水线模数转换器。通过采用自举开关和增益提升的套筒式共源共栅运放,保证了采样保持电路和级电路的性能。该模数转换器采用TSMC0.35μmCMOS3.3 V工艺流片验证,芯片核心面积为5.6 mm2。测试结果表明,该模数转换器在采样率为40 MHz输入频率为280 kHz时,获得54.5 dB的信噪比和60.2 dB的动态范围;在采样率为46 MHz输入频率为12.6 MHz时,获得52.1 dB的信噪比和60.6 dB的动态范围。
A 10 bit 40 MS / s pipeline ADC is designed. The performance of the sample-and-hold and stage circuits is guaranteed by the use of a bootstrapped switch and gain-boosted sleeve cascode. The analog-to-digital converter is verified with a TSMC 0.35μm CMOS 3.3 V process chip with a core area of 5.6 mm2. The test results show that the ADC achieves a signal-to-noise ratio of 54.5 dB and a dynamic range of 60.2 dB at an input frequency of 280 kHz at a sampling rate of 40 MHz. At an input frequency of 12.6 MHz at a sampling rate of 46 MHz, 52.1 dB SNR and 60.6 dB dynamic range.