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基于65nm CMOS工艺,设计了一种新型的CMOS主从式采样/保持电路。采用全差分开环主从式的双通道采样结构,提高了电路的线性度。采用负电压产生技术,解决了纳米级工艺下电源电压低的问题。采用Cadence Spectre软件对电路进行仿真分析。仿真结果显示,在1.9V电源电压、相干采样下,当输入频率为1.247 5GHz,峰-峰值为0.4V的正弦波信号,采样率为2.5GS/s,负载为0.8pF时,电路的无杂散动态范围(SFDR)为78.31dB,总谐波失真(THD)为-75.69dB,有效位为11.51位,可用于超高速A/D转换器中。
Based on the 65nm CMOS process, a new CMOS master-slave sampling / holding circuit is designed. The use of fully differential open-loop master-slave dual-channel sampling structure to improve the linearity of the circuit. The use of negative voltage generation technology to solve the problem of low power supply voltage in the nano-scale process. Cadence Specter software was used to simulate the circuit. The simulation results show that when the input frequency is 1.247 5GHz and the peak-to-peak value is 0.4V, the sampling rate is 2.5GS / s at 1.9V supply voltage and coherent sampling. When the load is 0.8pF, The dispersion dynamic range (SFDR) is 78.31dB, the total harmonic distortion (THD) is -75.69dB and the effective bit is 11.51 bits, which can be used in very high speed A / D converters.