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为了解决上下文自适应二进制算术编码器(CABAC,Context-based Adaptive Binary Arithmetic Coder)硬件实现吞吐率难以提高的问题,提出了基于数据流动态特性的电路优化方法.通过建立算法的数据流模型,提取出限制硬件实现性能的数据流反馈环路.针对上下文环路,采用3条迭代周期不同的子环路更新具有不同依赖周期的上下文变量,提高了时钟频率和吞吐率;对于字节打包环路,通过提取一类可简化电路结构的数据元素,并为之构建快速旁路,增加了环路的处理速度.基于上述方法并辅以基本的电路优化手段,设计实现在现场可编程门阵列(FPGA,Field-Programmable Gate Array)平台上频率可达309MHz,并且每个时钟周期处理一个编码符号.
In order to solve the problem that it is difficult to improve the throughput of context-based adaptive binary arithmetic coder (CABAC), a circuit optimization method based on the dynamic characteristics of data streams is proposed. By building the algorithm’s data flow model, A data flow feedback loop that limits the performance of the hardware is implemented. For the context loop, three different subloops with different iteration periods are used to update the context variables with different dependency periods to improve the clock frequency and throughput; for the byte packing loop , By extracting a class of data elements that can simplify the circuit structure and building a quick bypass for it, increasing the processing speed of the loop.Based on the above method and supplemented by the basic circuit optimization means, designed and implemented in the field programmable gate array FPGA, Field-Programmable Gate Array) platform frequency up to 309MHz, and each clock cycle to deal with a code symbol.