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工艺映射是FPGA设计中的关键技术，目前的研究目标是面积最小化，延时最小化和延时限制下面积最小化．然而，对任一给定的FPGA芯片，其面积大小是固定的．在固定的面积下求延时最小化工艺映射是FPGA设计中必须研究的新课题，本文首次给出这方面的成果．
Process mapping is the key technology in FPGA design. The current research goal is to minimize the area, minimize the delay and minimize the area under the delay limit. However, the size of any given FPGA chip is fixed. Minimizing latency in a fixed area Process mapping is a new topic that must be studied in FPGA design. This paper presents the first results in this area.