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本文介绍一种带衬底偏压发生器的5伏单电源64K动态RAM,其周期时间为300毫微秒时的典型功耗170毫瓦,典型的存取时间为120毫微秒,芯片面积为25.8平方毫米。为防止软差错,采用了芯片复盖技术。 (?)对贮存器稳定工作很重要的信噪比和衬底耦合噪声ΔV_(BB)的角度研究了图1中读放的三种安排方法。结果选择了图1所示的叠合数据线法。这种设计减小了数据线通过结电容产生的衬底耦合噪声,该噪声在衬底噪声源中是主要的。此外,还能作到数据线电容小及令人满意的共态噪声抑制。而且,版图还具有接触孔和扩散区的对准和改进单元结构的特点。这就减小了数据线电容,尤其是结电容和存贮单元的大电容,它也提高了信噪比。外通电路也作了仔细安排,以减小结电容,并消除衬底至读出放大器等微分型电路之间的耦合噪声。表1为估计的ΔV_(BB)。
This article describes a 5-volt, single-supply, 64K dynamic RAM with a substrate bias generator with a typical power dissipation of 170 milliwatts at a 300 nanosecond cycle time and a typical access time of 120 nanoseconds. The chip area It is 25.8 square millimeters. To prevent soft errors, using a chip cover technology. (?) Storage stability is very important for the work of the signal to noise ratio and substrate coupling noise ΔV_ (BB) point of view of the read and write in Figure 1 three arrangements. As a result, the data line method shown in FIG. 1 was selected. This design reduces the substrate coupling noise of the data lines through the junction capacitance, which is dominant in the substrate noise source. In addition, small data line capacitance can be achieved and satisfactory state noise suppression. Moreover, the layout also has the features of aligning the contact holes and diffusion regions and improving the cell structure. This reduces the data line capacitance, especially the junction capacitance and the large capacitance of the memory cell, which also increases the signal-to-noise ratio. The pass-through circuit is also carefully arranged to reduce the junction capacitance and eliminate the coupling noise between the substrate and the differential type circuit such as the sense amplifier. Table 1 shows the estimated ΔV_ (BB).