论文部分内容阅读
对于设计像 MPEG2视频解码器的复杂系统 ,关键的难点是其系统结构的设计。文中设计了一种适合 VL SI实现的 MPEG2解码器的系统结构。它支持 MPEG2 (MP@ML)码流 ,并且兼容 MPEG1码流。为了设计和优化这个结构 ,采用硬件描述语言 VHDL 设计了系统级的 MPEG2视频解码器。此解码器在 Viewlogic系统中进行了模拟 ,并且对一些码流进行了测试验证。
The key challenge for designing complex systems like MPEG2 video decoders is the design of their system architecture. In this paper, we design a system structure of MPEG2 decoder suitable for VLSI implementation. It supports MPEG2 (MP @ ML) code stream, and compatible with MPEG1 code stream. In order to design and optimize this structure, the system-level MPEG2 video decoder is designed by hardware description language VHDL. This decoder was simulated in Viewlogic system, and some code streams were tested and verified.