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Intel在旧金山召开的Inter-national Solid-State CircuitsConference会上发布P6技术细节和展示样品时将披露一些围绕P6的神秘外衣。 据报道,Intel随P6推出的一些关键设计变化包括128位的外部总线、集成到处理器封装内的二级高速缓冲以及将x86代码转换(翻译)成类RISC MicroOps的转换处理器。后者将提高现有应用系统的性能而无需重新编译。 一位给Pentium处理器进行汇编代码编程并熟悉P6的消息人士说:“Pentium没有任何这样的翻译硬件,它庄x86发展过程中是
Intel will reveal some of the mysterious garments surrounding the P6 when it unveiled P6 technical details and samples at the Inter-national Solid-State Circuits Conference in San Francisco. Some of the key design changes Intel introduced with P6 are reported to include a 128-bit external bus, L2 cache integrated into the processor package, and conversion processors that translate (translate) x86 code into RISC MicroOps. The latter will improve the performance of existing applications without having to recompile. A source who wrote the programming code for the Pentium processor and was familiar with P6 said: "The Pentium does not have any such translation hardware,