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普通锁相环路中,同步性能与捕获性能对环路设计的要求是矛盾的,需采用一些辅助方法来改善其捕获性能。常用的办法有采用非线性环路滤波器、在压控振荡器上加扫描电压或注入信号以及结合鉴频环路使用。本文研究将正弦鉴相特性进行非线性校正之后对环路捕获性能的影响,导出了经非线性校正后的等效鉴相特性以及由此构成的一、二阶环的性能。分析表明,校正后仍能保持原有环路的同步性能,同时却能明显地加宽捕捉带、缩短捕捉时间。对鉴相特性实施非线性校正是改善锁相环路捕获性能的有效途径,如何寻找更易于实现更有效的非线性函数,还值得进一步探讨。
In general PLLs, the synchronization performance and the acquisition performance are conflicting to the loop design requirements. Some auxiliary methods are needed to improve their acquisition performance. Commonly used methods have adopted non-linear loop filter, the voltage-controlled oscillator plus scan voltage or injection signal and the use of frequency loop. In this paper, we study the effect of sinusoidal phase discrimination on the loop acquisition performance after nonlinear correction, and derive the equivalent phase discrimination after nonlinear correction and the performance of the first and second order rings. The analysis shows that after the calibration, the synchronization performance of the original loop can be maintained, at the same time, the capture band can be obviously widened and the capture time can be shortened. It is an effective way to improve the acquisition performance of phase-locked loop by implementing the non-linear correction of the phase characteristics. It is worth further exploring how to find a more effective non-linear function.