对于使用双金属栅结构的 CMOS器件而言,是否能够成功的将这项工艺进行集成整合取决于工程师们对硬掩膜技术以及化学湿法刻蚀试剂的正确选择。本文比较了采用不同清洗工艺的多种成膜技术,以及基于上述技术得到的有效栅氧厚度(EOT)和其它相关电学参数的表现。 For CMOS devices using bimetallic gate structures, the successful integration of this process depends on the correct choice of hardmask technology and chemical wet etching reagents. This article compares various film-forming techniques using different cleaning processes, as well as the performance of effective gate oxide thickness (EOT) and other related electrical parameters based on these techniques.