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3D集成技术包括晶圆级、芯片与晶圆、芯片与芯片工艺流程,通过器件的垂直堆叠得到其性能的提升,并不依赖于基板的尺寸和技术。所有的报道均是传输速度提高,功耗降低,性能更好及更小的外形因素等优势使得这种技术的名气大振。选择晶圆或芯片级集成的决定应基于几个关键因素的考虑。对于不同种类CMOS、非CMOS器件间的集成,芯片尺寸不匹配引发了衬底的变化(如300mm对150mm).芯片与晶圆或芯片与芯片的堆叠也许是唯一的选择。另外,当芯片的成品率明显地不同于晶圆与晶圆键合方法时,在堆叠的晶圆中难以使确认好芯片的量达到最大。在这种情况下,应将一枚或两枚晶圆划切成小芯片并仅将合格的芯片垂直地集成。只要适当地采用晶圆与晶圆键合工艺便可实现高成品率器件同类集成。晶圆间键合具有最高的生产效率,工艺流程简便及最小的成本。满足选择晶圆级或芯片级工艺总的工艺解决方案应结合对准和键合细节来考虑决定最终的设备选择和工艺特性。所有这些工艺的论证证实对于多数产品的制造3D集成是可行的,而且有些也已成为生产的主流。
3D integration technologies include wafer level, chip and wafer, chip and chip process flow, and their performance is enhanced through vertical stacking of devices, independent of substrate size and technology. All of the reports are due to advances in transmission speed, lower power consumption, better performance, and smaller form factors that make this technology fame. The choice of wafer or chip level integration should be based on several key considerations. Substrate-to-chip mismatch induces substrate variations (eg, 300mm vs. 150mm) for the integration between different types of CMOS and non-CMOS devices. A chip-to-wafer or chip-to-chip stack may be the only choice. In addition, when the yield of a chip is significantly different from the wafer-to-wafer bonding method, it is difficult to maximize the amount of confirmed chips in stacked wafers. In this case, one or two wafers should be sliced into small chips and only the qualified chips should be vertically integrated. As long as the proper use of wafer and wafer bonding process can achieve the same high-yield device integration. Wafer bonding has the highest production efficiency, process simplicity and the lowest cost. Satisfying the choice of wafer level or chip level process The total process solution should be combined with alignment and bonding details to consider the final device selection and process characteristics. The demonstration of all these processes confirms that 3D integration is most feasible for most products, and some of them have also become the mainstream of production.