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基于SMIC 65nm CMOS工艺,设计了一种10位120 MS/s逐次逼近A/D转换器。电路为1.2V电源供电,采用基于单调转换方式的改进型低功耗D/A电容阵列,相比于传统电容阵列,功耗降低了91%。采用一级动态预放大加一级动态锁存器的动态比较器,以降低功耗和提高速度。设计了与电容阵列工作方式相结合的异步逻辑控制电路,以降低外部时钟设计难度,并在控制功耗的前提下提高速度。Spectre仿真验证结果表明,在采样频率为120 MHz,输入信号频率为60 MHz时,SFDR达到81.07dB,有效位数大于9位,具有良好的动态性能。电路整体功耗约为600μW。
Based on the SMIC 65nm CMOS process, a 10-bit 120 MS / s successive approximation A / D converter is designed. The circuit operates from a 1.2V supply and uses an improved low-power D / A capacitor array based on a monotonic conversion mode, which consumes 91% less power than a traditional capacitor array. Using a dynamic pre-amplification plus a dynamic latch dynamic comparator, to reduce power consumption and increase speed. An asynchronous logic control circuit is designed which combines with the working mode of the capacitor array to reduce the difficulty of designing the external clock and improve the speed under the premise of controlling the power consumption. Specter simulation results show that the SFDR achieves 81.07dB and the effective number of bits is greater than 9 when the sampling frequency is 120 MHz and the input signal frequency is 60 MHz. It has good dynamic performance. The overall power consumption of the circuit is about 600μW.