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设计了基于1T1R结构的16kb相变存储器(PCRAM)芯片及其版图。芯片包括存储阵列、外围读写控制电路、纠错电路(ECC)、静电防护电路(ESD)。版图上对纳米存储单元(1R)与CMOS工艺的融合作了优化处理,给出了提高存储单元操作电流热效率的具体方法。1R位于顶层金属(TM)和二层金属(TM-1)之间,包含存储材料以及上下电极,需要在传统CMOS工艺基础上添加掩膜版。读出放大器采用全对称的差分拓扑结构,大大提升了抗干扰能力、灵敏精度以及读出速度。针对模块布局、电源分配、二级效应等问题,给出了版图解决方案。采用中芯国际130nm CMOS工艺流片,测试结果显示芯片成品率(bit yield)可达99.7%。
A 16kb phase change memory (PCRAM) chip based on 1T1R structure and its layout are designed. The chip includes a memory array, a peripheral read-write control circuit, an error correction circuit (ECC), and an electrostatic protection circuit (ESD). The layout of the nano-memory cell (1R) and CMOS technology for the integration of the optimization process is given to improve the thermal efficiency of the memory cell operating current specific methods. The 1R, located between the top metal (TM) and the second metal (TM-1), contains the memory material as well as the top and bottom electrodes and requires the addition of a mask on top of the traditional CMOS process. The sense amplifier uses a fully symmetrical differential topology, greatly improving the anti-interference ability, sensitivity and read speed. For the module layout, power distribution, two effects and other issues, given the layout solution. The use of SMIC 130nm CMOS process chip, the test results show that the chip yield (bit yield) up to 99.7%.