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This paper concerns a decoding strategy to improve the throughput in NAND flash memory using lowdensity parity-check(LDPC) codes. As the reliability of NAND flash memory continues degrading, conventional error correction codes have become increasingly inadequate.LDPC code is highly desirable, due to its powerful correction strength. However, in order to maximize the correction strength, LDPC codes demand fine-grained memory sensing,leading to a significant read latency penalty. To address the drawbacks caused by soft-decision LDPC decoding, this paper proposes a hybrid hard-/soft-decision LDPC decoding strategy. Simulation results show that the proposed approach could reduce the read latency penalty and hence improve the decoding throughput up to 30 %, especially in early lifetime of NAND flash memory, compared with the conventional decoding with equivalent area.
This paper concerns a decoding strategy to improve the throughput in NAND flash memory using low density parity-check (LDPC) codes. As the reliability of NAND flash memory continued degrading, conventional error correction codes have become increasingly worsquate. LDPC code is highly desirable, due To its powerful correction strength. However, in order to maximize the correction strength. LDPC codes demand fine-grained memory sensing, leading to a significant read latency penalty. To address the drawbacks caused by soft-decision LDPC decoding, this paper vi Simulation results show that the proposed approach could reduce the read latency penalty and hence improve the decoding throughput up to 30%, especially in early flash of NAND flash memory, compared with the conventional decoding with equivalent area.