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This paper presents an 11-bit 22-MS/s 0.6-mW successive approximation register(SAR) analog-todigital converter(ADC) using SMIC 65-nm low leakage(LL) CMOS technology with a 1.2 V supply voltage. To reduce the total capacitance and core area the split capacitor architecture is adopted. But in high resolution ADCs the parasitic capacitance in the LSB-side would decrease the linearity of the ADC and it is hard to calibrate. This paper proposes a parasitic capacitance compensation technique to cancel the effect with no calibration circuits.Moreover, dynamic circuits are used to minimize the switching power of the digital logic and also can reduce the latency time. The prototype chip realized an 11-bit SAR ADC fabricated in SMIC 65-nm CMOS technology with a core area of 300 200 m2. It shows a sampling rate of 22 MS/s and low power dissipation of 0.6 mW at a1.2 V supply voltage. At low input frequency the signal-to-noise-and-distortion ratio(SNDR) is 59.3 dB and the spurious-free dynamic range is 72.2 dB. The peak figure-of-merit is 36.4 fJ/conversion-step.
This paper presents an 11-bit 22-MS / s 0.6-mW two-way approximation register (SAR) analog-todigital converter (ADC) using SMIC 65-nm low leakage (LL) CMOS technology with a 1.2 V supply voltage. total capacitance and core area the split capacitor architecture is adopted. This paper proposes a parasitic capacitance compensation technique to cancel the effect with no calibration circuits. Moreover, dynamic circuits are used to minimize the switching power of the digital logic and also can reduce the latency time. The prototype chip realized an 11-bit SAR ADC fabricated in SMIC 65-nm CMOS technology with a core It shows a sampling rate of 22 MS / s and low power dissipation of 0.6 mW at a 1.2 V supply voltage. At low input frequency the signal-to-noise-and-distortion ratio (SNDR) is 59.3 dB and the spurious-free dynamic ran ge is 72.2 dB. The peak figure-of-merit is 36.4 fJ / conversion-step.