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1 前言关于 LSI 的高密度化,现以 DRAM 为例来说,则是从16M 开始至64M 出厂样品。对于逻辑电路来说,0.5μm 级的产品化正在开始。在 DRAM 中至256M 布线层数已达到3层,在逻辑系列器件中,自0.4μm 级以后,考虑到需要有4层到6层的多层布线技术,在横向高密度化的同时,向纵向方面的结构扩大问题就变得很重要了。电极布线形成技术其重要性在日益增加的同时也变得日渐复杂起来。另一方面,布线结构的多层化、复杂化,在其较难实现的同时,也招致 LSI 芯片成本的增大,这在 LSI 制造的整个成本中已占有了不可忽视的一部分。
1 Introduction About LSI’s density, now DRAM, for example, is from 16M to 64M factory samples. For logic circuits, the 0.5μm level of product is starting. In the DRAM to 256M wiring layer has reached three layers in the logic devices, since the 0.4um level, considering the need to have four to six layers of multi-layer wiring technology, in the horizontal high-density at the same time, to the vertical The problem of structural expansion becomes important. The importance of electrode wire formation technology is also growing increasingly complicated. On the other hand, multi-layer wiring structure, more complex, in its more difficult to achieve, but also lead to LSI chip costs increase, which LSI manufacturing costs have accounted for an integral part of can not be ignored.