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Abstract: This paper presents modified version of a realistic test tool suitable to Design For Testability (DFT) and Built-In Self Test(BIST) environments. A comprehensive tool is developed in the form of a test simulator. The simulator is capable of providing a required goal of test for the Circuit Under Test (CUT). The simulator uses the approach of fault diagnostics with fault grading procedures to provide the optimum tests. The current version of the simulator embeds features of exhaustive and pseudo-random test generation schemes along with the search solutions of cost effective test goals. The simulator provides facilities of realizing all possible pseudo-random sequence generators with all possible combinations of seeds. The tool is developed on a common Personal Computer(PC) platform and hence no special software is required. Thereby, it is a low cost tool hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any CUT. The developed tool incorporates flexible Graphical User Interface (GUI) procedures and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safe-reliable-testable digital logic designs.
Key words: Digital system testing, built-in self test, design for testability, test vector, pseudo-random test sequence, linear feedback shift registers, fault diagnosis, fault collapsing, realistic test, fault cover, iteration.
1. Introduction
The rapid development in electronic circuits and the advances in semiconductor technology led to increased Integrated Circuit (IC) densities. This led to a decrease in cost of these circuits and an increase in the performance. However as a consequence of higher integration densities, these circuits have become very complex. To verify the correct functioning, these circuits are required to be thoroughly tested. The test cost of even a Large Scale Integration (LSI) circuit is a substantial portion of the overall production cost. In addition, the advances in IC technology are occurring in a rate faster than those in testing technology. A direct consequence of this is a non conformity between the development of the test technology and the increase of the IC densities [1-3].
Formal Design For Testability (DFT) techniques are concerned with providing access points for testing (i.e., enhancing controllability and observability in ICs)[4-5]. Currently, DFT and BIST (Built-In Self Test) have become effective and widely acceptable tools for tackling test problems for Very Large Scale Integration(VLSI) chips and systems [6]. This is because of the inherent advantages of DFT and BIST techniques [6]. However, any technique chosen must be incorporated within the framework of a powerful Computer Aided Designed (CAD) system providing semi-automatic analysis and feedback, such that the Rule of Ten can be kept under control: If one does not find a failure at a particular stage, then detection at the next stage will cost 10 times as much [3]!
Testability is a measure to determine a desired degree of accuracy with which the functionality of any system or circuit or component can operate. A very high cost of test, and an uncertain level of delivered system quality are the indirect costs of non DFT design testability. Further, adding the time spent trying to diagnose the fault makes a non DFT design very expensive. When testability is introduced at the design stage, it dramatically lowers the cost of test and the time spent at test. Properly managed, testability enhances the assurance of product quality and smoothes production scheduling assuring high availability of service, and less maintenance cost [7].
Since testability is not a technological innovation therefore, with preparedness of a mindset that motivates and creates a constant awareness of the importance of ease-of-testing at all levels of developments and use of the systems. In real sense, it can be said testability is a very critical parameter to the manufacturing process of any system and a system that cannot be readily tested is not really to be considered as manufacturable engineering [7].
Further elongating the problem of testing is at present, in general most system designers and electronics engineers have little knowledge about testing, and thus the companies frequently hire test technology experts to guide their designers on test problems and the companies are even bound to pay higher remunerations to the test experts than to the total gross salaries of their designers. This reflects also today’s university education and their designed curriculum. Due to this weakness of designed curriculum everyone learns about design, but only truly dedicated students learn about test. The next generation of engineers involved with design technology should be made aware of the importance of test and trained in test technology to enable them to produce high quality and defect-free products [7-9].
References
[1] A. Ahmad, J. Al-Balushi, Study to investigate the impact of combining response data compression techniques for built-in self test, in: Proceedings of International Conference on Computing and Information Technology(ICCIT 2012), pp. 665-669.
[2] A. Ahmad, On a design approach for reducing aliasing errors and achieving higher testability goals in combinational circuits, Ph.D. Thesis, Indian Institute of Technology, Roorkee, 1989.
[3] A. Ahmad, Testing of complex integrated circuits(ICs)—The bottlenecks and solutions, Asian Journal of Information Technology 4 (9) (2005) 816-822.
[4] A.M.J. Al-Lawati, A. Ahmad, Realization of a simplified controllability computation procedure—A MATLAB-SIMULINK based tool, Journal for Scientific Research: Science and Technology 8 (2004) 131-143.
[5] A. Ahmad, A.M.J. Al-Lawati, A.M. Al-Naamany, Identification of test point insertion location via comprehensive knowledge of digital system’s nodal controllability through a simulated tool, Asian Journal of Information Technology 3 (3) (2004) 142-147.
[6] Y. Zorian, S. Mourad, Principles of Testing Electronic Systems, J. Wiley & Sons, New York, 2000, p. 420.
[7] A. Ahmad, D. Al-Abri, Design of an optimal test simulator for built-in self test environment, Journal of Engineering Research 7 (2) (2010) 69-79.
[8] E. Ivask, J. Raik, R. Ubar, Comparison of genetic and random techniques for test pattern generation, in: Proceedings of the 6th Baltic Electronics Conference, 1998, pp. 163-166.
[9] R. Ubar, H.D. Wuttke, The Dildis-project—Using applets for more demonstrative lectures in digital systems design and test, in: 31st Annual Frontiers in Education Conference, Reno, NV, USA, October 10-13, 2001.
[10] S. Devadze, A. Jutman, A. Sudnitsyn, R. Ubar, H.D. Wuttke, Teaching digital RT-level self-test using a Java applet, in: Proceedings of 20th IEEE Conference NORCHIP’2002, pp. 322-328.
[11] L. Ali, R. Sidek, I. Aris, M.A.M. Ali, B.S. Suparjo, Design of a low cost IC tester, American Journal of Applied Science 2 (4) (2005) 824-827.
[12] A. Ahmad, D. Al-Abri, M.M. Al-Ramhi, Design of an e-learning process in the area of digital system testing, in: Proceedings of International Conference on Distance Education (ICODE2006), pp. 1-8.
[13] A. Ahmad, D. Al-Abri, Design of dynamic test tool in the area of digital system testing, in: Proceedings of International Conference on Computer, Communication and Power (ICCCP’09), 2009, pp. 1-4.
[14] M.C. Hansen, H. Yalcin, J.P. Hayes, Unveiling the ISCAS-85 benchmarks: A case study in reverse engineering, IEEE Design & Test 16 (3) 72-80.
[15] A. Ahmad, D. Al-Abri, Design of a pseudo-random binary code generator via a developed simulation model, in: Proceedings 2nd International Joint Conference on Advances in Engineering and Technology-Advances in Electrical and Electronics (AET-AEE), 2011, pp. 88-91.
[16] A. Ahmad, A. Al-Maashri, Investigating some special sequence length generated in an external exclusive-NOR type LFSR, Computers and Electrical Engineering 34(2008) 270-280.
[17] A. Ahmad, Investigation of typical properties of some LFSR structures, Journal of System Science and Engineering 17 (1) (2008) 65-69.
[18] A. Ahmad, M.J. Al-Musharafi, S. Al-Busaidi, A new algorithmic procedure to test m-sequences generating feedback connections of stream cipher’s LFSRs, in: Proceedings of IEEE Conference on Electrical and Electronic Technology (TENCON’01), 2001, Vol. 1, pp. 366-369.
[19] A. Ahmad, A.M. Elabdalla, An efficient method to determine linear feedback connections in shift registers that generate maximal length pseudo-random up and down binary sequences, Computer & Electrical Engineering 23(1) (1997) 33-39.
Key words: Digital system testing, built-in self test, design for testability, test vector, pseudo-random test sequence, linear feedback shift registers, fault diagnosis, fault collapsing, realistic test, fault cover, iteration.
1. Introduction
The rapid development in electronic circuits and the advances in semiconductor technology led to increased Integrated Circuit (IC) densities. This led to a decrease in cost of these circuits and an increase in the performance. However as a consequence of higher integration densities, these circuits have become very complex. To verify the correct functioning, these circuits are required to be thoroughly tested. The test cost of even a Large Scale Integration (LSI) circuit is a substantial portion of the overall production cost. In addition, the advances in IC technology are occurring in a rate faster than those in testing technology. A direct consequence of this is a non conformity between the development of the test technology and the increase of the IC densities [1-3].
Formal Design For Testability (DFT) techniques are concerned with providing access points for testing (i.e., enhancing controllability and observability in ICs)[4-5]. Currently, DFT and BIST (Built-In Self Test) have become effective and widely acceptable tools for tackling test problems for Very Large Scale Integration(VLSI) chips and systems [6]. This is because of the inherent advantages of DFT and BIST techniques [6]. However, any technique chosen must be incorporated within the framework of a powerful Computer Aided Designed (CAD) system providing semi-automatic analysis and feedback, such that the Rule of Ten can be kept under control: If one does not find a failure at a particular stage, then detection at the next stage will cost 10 times as much [3]!
Testability is a measure to determine a desired degree of accuracy with which the functionality of any system or circuit or component can operate. A very high cost of test, and an uncertain level of delivered system quality are the indirect costs of non DFT design testability. Further, adding the time spent trying to diagnose the fault makes a non DFT design very expensive. When testability is introduced at the design stage, it dramatically lowers the cost of test and the time spent at test. Properly managed, testability enhances the assurance of product quality and smoothes production scheduling assuring high availability of service, and less maintenance cost [7].
Since testability is not a technological innovation therefore, with preparedness of a mindset that motivates and creates a constant awareness of the importance of ease-of-testing at all levels of developments and use of the systems. In real sense, it can be said testability is a very critical parameter to the manufacturing process of any system and a system that cannot be readily tested is not really to be considered as manufacturable engineering [7].
Further elongating the problem of testing is at present, in general most system designers and electronics engineers have little knowledge about testing, and thus the companies frequently hire test technology experts to guide their designers on test problems and the companies are even bound to pay higher remunerations to the test experts than to the total gross salaries of their designers. This reflects also today’s university education and their designed curriculum. Due to this weakness of designed curriculum everyone learns about design, but only truly dedicated students learn about test. The next generation of engineers involved with design technology should be made aware of the importance of test and trained in test technology to enable them to produce high quality and defect-free products [7-9].
References
[1] A. Ahmad, J. Al-Balushi, Study to investigate the impact of combining response data compression techniques for built-in self test, in: Proceedings of International Conference on Computing and Information Technology(ICCIT 2012), pp. 665-669.
[2] A. Ahmad, On a design approach for reducing aliasing errors and achieving higher testability goals in combinational circuits, Ph.D. Thesis, Indian Institute of Technology, Roorkee, 1989.
[3] A. Ahmad, Testing of complex integrated circuits(ICs)—The bottlenecks and solutions, Asian Journal of Information Technology 4 (9) (2005) 816-822.
[4] A.M.J. Al-Lawati, A. Ahmad, Realization of a simplified controllability computation procedure—A MATLAB-SIMULINK based tool, Journal for Scientific Research: Science and Technology 8 (2004) 131-143.
[5] A. Ahmad, A.M.J. Al-Lawati, A.M. Al-Naamany, Identification of test point insertion location via comprehensive knowledge of digital system’s nodal controllability through a simulated tool, Asian Journal of Information Technology 3 (3) (2004) 142-147.
[6] Y. Zorian, S. Mourad, Principles of Testing Electronic Systems, J. Wiley & Sons, New York, 2000, p. 420.
[7] A. Ahmad, D. Al-Abri, Design of an optimal test simulator for built-in self test environment, Journal of Engineering Research 7 (2) (2010) 69-79.
[8] E. Ivask, J. Raik, R. Ubar, Comparison of genetic and random techniques for test pattern generation, in: Proceedings of the 6th Baltic Electronics Conference, 1998, pp. 163-166.
[9] R. Ubar, H.D. Wuttke, The Dildis-project—Using applets for more demonstrative lectures in digital systems design and test, in: 31st Annual Frontiers in Education Conference, Reno, NV, USA, October 10-13, 2001.
[10] S. Devadze, A. Jutman, A. Sudnitsyn, R. Ubar, H.D. Wuttke, Teaching digital RT-level self-test using a Java applet, in: Proceedings of 20th IEEE Conference NORCHIP’2002, pp. 322-328.
[11] L. Ali, R. Sidek, I. Aris, M.A.M. Ali, B.S. Suparjo, Design of a low cost IC tester, American Journal of Applied Science 2 (4) (2005) 824-827.
[12] A. Ahmad, D. Al-Abri, M.M. Al-Ramhi, Design of an e-learning process in the area of digital system testing, in: Proceedings of International Conference on Distance Education (ICODE2006), pp. 1-8.
[13] A. Ahmad, D. Al-Abri, Design of dynamic test tool in the area of digital system testing, in: Proceedings of International Conference on Computer, Communication and Power (ICCCP’09), 2009, pp. 1-4.
[14] M.C. Hansen, H. Yalcin, J.P. Hayes, Unveiling the ISCAS-85 benchmarks: A case study in reverse engineering, IEEE Design & Test 16 (3) 72-80.
[15] A. Ahmad, D. Al-Abri, Design of a pseudo-random binary code generator via a developed simulation model, in: Proceedings 2nd International Joint Conference on Advances in Engineering and Technology-Advances in Electrical and Electronics (AET-AEE), 2011, pp. 88-91.
[16] A. Ahmad, A. Al-Maashri, Investigating some special sequence length generated in an external exclusive-NOR type LFSR, Computers and Electrical Engineering 34(2008) 270-280.
[17] A. Ahmad, Investigation of typical properties of some LFSR structures, Journal of System Science and Engineering 17 (1) (2008) 65-69.
[18] A. Ahmad, M.J. Al-Musharafi, S. Al-Busaidi, A new algorithmic procedure to test m-sequences generating feedback connections of stream cipher’s LFSRs, in: Proceedings of IEEE Conference on Electrical and Electronic Technology (TENCON’01), 2001, Vol. 1, pp. 366-369.
[19] A. Ahmad, A.M. Elabdalla, An efficient method to determine linear feedback connections in shift registers that generate maximal length pseudo-random up and down binary sequences, Computer & Electrical Engineering 23(1) (1997) 33-39.