The key technologies for the dual high-k and dual metal gate,such as the electrical optimization of metal insert poly-Si stack structure,the separating of high-k and metal gate of n/pMOS in different regions of the wafer,and the synchronous etching of n/pMOS gate stack,are successfully developed.First,reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiOx.Then,the separating of high-k and metal gate for n/pMOS is achieved by SC1(NH4OH:H2O2:H2O = 1 : 1 : 5)and DHF-based solution for the selective removing of nMOS TaN and HfSiON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON.After that,the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate.Finally,good electrical characteristics of CMOS devices,obtained by utilizing these new developed technologies,further confirm that they are practicable technologies for DHDMG integration.