通过对现有几种闩锁比较器的分析和比较,提出一种应用于流水线ADC中改进的动态闩锁电压比较器结构,该结构具有较小的功耗和回踢噪声的特点。并采用0.18um CMOS1P6M工艺对电路进行设计,在电源电压为1.8V的条件下,对电路进行仿真,仿真结果表明它的回踢噪声小,输入敏感电压误差小于2mV,最高工作频率200MHz,功耗270uW。 By analyzing and comparing several existing latch comparators, an improved dynamic latch voltage comparator structure is proposed for pipeline ADC, which has the advantages of low power consumption and kickback noise. The circuit is designed with 0.18um CMOS1P6M process. The circuit is simulated under the supply voltage of 1.8V. The simulation results show that the back-kick noise is small, the input sensitive voltage error is less than 2mV, the maximum operating frequency is 200MHz, the power consumption 270uW.