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在传统集成电路(IC)的低功耗设计方法基础上,提出3种低功耗技术,并实现无线传感网传感器节点,作为实例验证。在系统级,提出联合编译技术的优化策略以及为无线传感网提供特殊低功耗模式的硬件架构。在电路级,基于集成电路算子设计方法学,考虑到在算法映射阶段时钟布局,提出时钟算子。以上技术均通过一个无线传感网传感器节点的低功耗设计实例来验证。测试结果显示,使用新提出的3种方法,在深度睡眠模式下,传感器节点芯片功耗为167μW,板级功耗可以达到1.035 mW。
Based on the low power consumption design method of traditional integrated circuit (IC), three kinds of low power consumption technologies are proposed, and the WSN sensor node is implemented as an example. At the system level, the optimization strategy of joint compilation technology and the hardware architecture of providing special low power consumption mode for wireless sensor network are proposed. At the circuit level, based on IC operator design methodology, a clock operator is proposed considering the clock layout at the algorithm mapping stage. The above techniques are verified by a low-power design example of a WSN sensor node. The test results show that with the newly proposed three methods, the sensor node chip consumes 167μW in power consumption and 1.035 mW in board-level power consumption in deep-sleep mode.