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Based on the coordinate rotation digital computer(CORDIC)algorithm,the high-speed kinematicscalculation for a six degree of freedom(DOF)space manipulator is implemented in a field programmablegate array(FPGA)co-processor.A pipeline architecture is adopted to reduce the complexity and time-consumption of the kinematics calculation .The CORDIC soft-core and the CORDIC-based pipelined kine-matics calculation co-processor are described with the very-high-speed integrated circuit hardware descrip-tion language(VHDL)language and realized in the FPGA .Finally,the feasibility of the design is vali-dated in the Spartan-3 FPGA of Xilinx Inc.,and the performance specifications of FPGA co-processor arediscussed.The results show that time-consumption of the kinematics calculation is greatly reduced.
Based on the coordinate rotation digital computer (CORDIC) algorithm, the high-speed kinematicscalculation for a six degree of freedom (DOF) space manipulator is implemented in a field programmablegate array (FPGA) co-processor. complexity and time-consumption of the kinematics calculation. CORDIC soft-core and the CORDIC-based pipelined kine-matics calculation co-processor are described with the very-high-speed integrated circuit hardware descriptive language (VHDL) language and realized in the FPGA. Finally, the feasibility of the design is vali-dated in the Spartan-3 FPGA of Xilinx Inc., and the performance specifications of FPGA co-processor are wasiscussed. The results show that time-consumption of the kinematics calculation is greatly reduced.