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本文针对 InAlAs/InGaAs InP基高电子迁移率晶体管(High electron mobility transistors, HEMTs)提出了一种结合高选择性湿法腐蚀和非选择性数字湿法腐蚀的两步栅槽腐蚀工艺。通过采用丁二酸和双氧水(H-_2O_2)混合溶液,InGaAs 与 InAlAs 材料的腐蚀选择比可以超过 100。该选择性湿法腐蚀工艺在 InAlAs/InGaAs InP 基 HEMTs 栅槽工艺中得到了很好的验证,栅槽腐蚀会自动终止在 InAl As势垒层。本文通过分离氧化/去氧化过程开发了非选择性数字湿法腐蚀工艺,每个周期能除去 1.2 nm InAlAs材料。最终,两步栅槽腐蚀工艺被成功用于器件制备中,数字湿法腐蚀重复两个周期去掉约3 nm InAlAs 势垒层材料。通过该方法制备的 InP基 HEMTs 器件比只依靠选择性湿法腐蚀栅槽工艺制备出的器件具有更短的栅沟间距,表现出更好的有效跨导和射频特性。
In this paper, a two-step gate trench etching process combining high selectivity wet etching with non-selective digital wet etching is proposed for InAlAs / InGaAs InP high electron mobility transistors (HEMTs). By using a mixed solution of succinic acid and hydrogen peroxide (H-2 O 2), the etching selectivity of InGaAs to InAlAs materials can exceed 100. The selective wet etching process is well verified in the InAlAs / InGaAs InP-based HEMTs gate trench process and the gate etch automatically terminates in the InAlAs barrier layer. In this paper, a non-selective digital wet etching process has been developed through a separate oxidation / deoxidation process that removes 1.2 nm of InAlAs material per cycle. Finally, a two-step gate trench etch process was successfully used for device fabrication. Digital wet etch removed about 3 nm of InAlAs barrier material for two cycles. The InP-based HEMTs fabricated by this method have a shorter gate-to-trench spacing than those fabricated by a selective wet etching of the gate trench and exhibit better effective transconductance and RF characteristics.