The tail bits of intermediate resistance states (IRSs) achieved in the SET process (IRSs) and the RESET process (IRSR) of conductive-bridge random-access memory were investigated.Two types of tail bits were observed,depending on the filament morphology after the SET/RESET operation.(i) Tail bits resulting from lateral diffusion of Cu ions introduced an abrupt increase of device resistance from IRS to ultrahigh-resistance state,which mainly happened in IRSs.(ii) Tail bits induced by the vertical diffusion of Cu ions showed a gradual shift of resistance toward lower value.Statistical results show that more than 95％ of tail bits are generated in IRSs.To achieve a reliable IRS for multilevel cell (MLC) operation,it is desirable to program the IRS in RESET operation.The mechanism of tail bit generation that is disclosed here provides a clear guideline for the data retention optimization of MLC resistive random-access memory cells.