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工艺的进步和消费电子市场对高密度非易失性存储的需求,促使多层单元闪存代替单层单元闪存成为闪存市场的主流,但同时提出数据可靠性的需求。针对多层单元闪存中存在的多比特随机错误问题,闪存控制器中需要实现低功耗高带宽的BCH编解码器。设计采用8 bit的并行编解码,每1 024 Byte能纠正32 bit的随机错误。关键方程步骤采用简化伯利坎普-梅西算法,优化逻辑。功能仿真和FPGA原型验证证明设计的正确性。
Advances in technology and consumer electronics market demand for high-density nonvolatile memory have driven the adoption of multi-level cell flash instead of single-level cell flash as the mainstream of the flash memory market, but at the same time, raised the need for data reliability. Aiming at the problem of multi-bit random errors in multi-level cell flash, a BCH codec with low power consumption and high bandwidth needs to be implemented in the flash memory controller. The design uses 8 bit parallel codec, every 1024 bytes can correct 32 bit random error. The key equation steps simplify the Burk-Kalman-Macy’s algorithm and optimize the logic. Functional simulation and FPGA prototype verification to prove the correctness of the design.