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不精确的广义门电路可靠性映射到门级或高层应用时误差容易因规模效应等而被过度放大导致结果不可靠.本文选择了在门级电路可靠性精确评估中得到有效验证的PTM模型用以精确计算晶体管级广义门电路的结构可靠性;分析了晶体管级广义门电路结构的逻辑抽象并转换成了功能一致的门级电路结构的逻辑抽象形式;提取了电路各组成单元的故障点及主要故障模式,并构建了与之相对应的面向故障的概率转移矩阵;依据各组成单元间的串并联特点,在有考虑输入信号故障的情况下,通过门级PTM方法的运算法则计算得到了晶体管级广义门电路的结构可靠性.在典型的CMOS广义门电路上的实验结果验证了本文所提方法的有效性,还分析了广义门电路的可靠性与其各主要类型故障之间的关系,并获得了一些有意义的结果.
Inaccurate generalized gate-to-gate reliability mapping to gate-level or high-level applications is easily over-amplified due to scale effects, etc., resulting in unreliable results.This paper selects PTM models that are validly validated for accurate gate-level circuit reliability estimates The structural reliability of the transistor-level generalized gate is accurately calculated. The logic abstraction of the transistor-level generalized gate is analyzed and converted into the logical abstract form of the gate-level structure with the same functions. The fault points of the constituent elements of the circuit are extracted, Main failure mode and corresponding fault-oriented probability transfer matrix. Based on the characteristics of series-parallel connection between the constituent elements, under the condition of considering the input signal failure, the algorithm of gate-level PTM method is calculated The structural reliability of the transistor-level generalized gate is tested in the typical CMOS generalized gate, which verifies the effectiveness of the proposed method and analyzes the relationship between the reliability of the generalized gate and its major types of faults. And got some meaningful results.