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在现代微处理器的设计中,CACHE是整个微处理器性能的决定性因素。本文详细介绍了32位RISC微处理器“龙腾”R2中指令CACHE的体系结构,着重研究了其设计和实现问题。为了提高性能,采用了预取技术和流水线技术来优化设计,仿真结果表明得到了预期的效果。
In the design of modern microprocessors, CACHE is a decisive factor in the overall microprocessor performance. This article describes in detail the 32-bit RISC microprocessor “Dragon” R2 instruction CACHE architecture, focusing on the design and implementation of its problems. In order to improve the performance, prefetch technology and pipeline technology are used to optimize the design. The simulation results show that the expected result is obtained.