At-speed testing using extal tester requires an expensive equiprnment, thus built-in self-test (BIST) is an altative technique due to its ability to rnperform on-chip at-speed self-testing. The main issue in BIST for at-speed testing rnis to obtain high delay fault coverage with a low hardware overhead. This parnper presents an improved loop-based BIST scheme, in which a configurable MISR rn(multiple-input signature register) is used to generate test-pair sequences. The strucrnture and operation modes of the BIST scheme are described. The topological properrnties of the state-transition-graph of the proposed BIST scheme are analyzed. Based rnon it, an approach to design and efficiently implement the proposed BIST scheme rnis developed. Experimental results on academic benchmark circuits are presented rnto demonstrate the effectiveness of the proposed BIST scheme as well as the design rnapproach.