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电磁干扰(EMI)是瞬时功能故障的主要来源之一,原因是电源供电线上的噪声注入引起了VDD和GND的额定值的波动.介绍了一种新的方法来增强片上系统(SoC)关于电源和接地电压瞬变时的信号完整性,并且这种方法完全符合IEC 61000—4—29标准.其基本思想是设计和IEC 61000—4—29兼容的集成电路,通过局部和动态地将时钟占空比去适应传播延迟的变化和扰动的逻辑路径.当无法满足时,该方法导致暂时把集成电路的工作频率减小到满足该标准的最小值.根据异常电网活动,时钟占空比调制(CDCM)是通过使用正和/或负边沿时钟展宽逻辑(CSL)块来实现的.基于这个概念,在尽可能保持时钟高速频率的同时,数字电路对于电源供电线上波动的耐受性将会更强.该方法可被视作一种在线提供动态自适应同步的监视技术.通过SPICE模拟,实验结果表明此方法的有效性.
Electromagnetic Interference (EMI) is one of the major sources of transient functional failures due to noise injection on the power supply line causing fluctuations in the nominal values of VDD and GND. A new method is introduced to enhance the on-chip system (SoC) Power and ground voltage transient signal integrity, and this method is fully in line with IEC 61000-4-29 standard.The basic idea is to design and IEC 61000-4-29 compatible integrated circuits, by local and dynamic clock Duty cycle to accommodate propagation delay variations and disturbances in a logical path that, when not met, results in a temporary reduction in the operating frequency of the integrated circuit to a minimum that satisfies the standard.According to anomalous grid activity, the clock duty cycle modulation (CDCM) is achieved by using positive and / or negative edge clock stretching logic (CSL) blocks. Based on this concept, the digital circuitry’s resistance to fluctuations in the power supply line while keeping the clock high speed as high as possible The method can be regarded as a monitoring technology that provides dynamic adaptive synchronization online.Experimental results show the effectiveness of this method by SPICE simulation.