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The positive bias temperature instability(PBTI) degradations of high-k/metal gate(HK/MG) n MOSFETs with thin Ti N capping layers(1.4 nm and 2.4 nm) are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI(90?C,125?C, 160?C) are studied and activation energy(Ea) values(0.13 e V and 0.15 e V) are extracted. Although the equivalent oxide thickness(EOT) values of two Ti N thickness values are almost similar(0.85 nm and 0.87 nm), the 2.4-nm Ti N one(thicker Ti N capping layer) shows better PBTI reliability(13.41% at 0.9 V, 90?C, 1000 s). This is due to the better interfacial layer/high-k(IL/HK) interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer.
The positive bias temperature instability (PBTI) degradations of high-k / metal gate (HK / MG) n MOSFETs with thin TiN capping layers (1.4 nm and 2.4 nm) are systematically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI (90 ° C, 125 ° C, 160 ° C) are studied and activation energy (Ea) values (0.13 eV and 0.15 e V) are Although the equivalent oxide thickness (EOT) values of two Ti N thickness values are almost similar (0.85 nm and 0.87 nm), the 2.4-nm Ti N one (thicker Ti N capping layer) shows better PBTI reliability (13.41% at 0.9 V, 90 μC, 1000 μs). This is due to the better interfacial layer / high-k (IL / HK) interface, and HK bulk states exhibits penetration of active energy and trap energy distribution in the high-k layer.